課程資訊
課程名稱
 邏輯合成與驗證
Logic Synthesis and Verification 
開課學期
 110-1 
授課對象
 電機資訊學院  電機工程學研究所  
授課教師
 江介宏 
課號
 EEE5028 
課程識別碼
 943 U0300 
班次
  
學分
 3.0 
全/半年
 半年 
必/選修
 選修 
上課時間
 星期三2,3,4(9:10~12:10) 
上課地點
 電二101 
備註
 總人數上限：30人 
Ceiba 課程網頁
 http://ceiba.ntu.edu.tw/1101LSV 
課程簡介影片
 
核心能力關聯
 核心能力與課程規劃關聯圖
課程大綱
為確保您我的權利,請尊重智慧財產權及不得非法影印
課程概述

Logic synthesis is an automated process of generating logic circuits satisfying certain Boolean constraints and/or transforming logic circuits with respect to optimization objectives. It is an essential step in the design automation of VLSI systems and is crucial in extending the scalability of formal verification tools. This course introduces classic logic synthesis problems and solutions as well as some recent developments. 

課程目標
 This course is intended to introduce Boolean algebra, Boolean function representation and manipulation, logic circuit optimization, circuit timing analysis, formal verification, and other topics. The students may learn useful Boolean reasoning techniques for various applications even beyond logic synthesis. 
課程要求
 The prerequisite is the undergrad "Logic Design" course. Knowledge about data structures and programming would be helpful. 
預期每週課後學習時數
  
Office Hours
  
指定閱讀
 待補 
參考書目
 * F. M. Brown. Boolean Reasoning: The Logic of Boolean Equations. Dover, 2003.

* S. Hassoun and T. Sasao. Logic Synthesis and Verification. Springer, 2001.

* G. D. Hachtel and F. Somenzi. Logic Synthesis and Verification Algorithms. Springer, 2006.

* W. Kunz and D. Stoffel. Reasoning in Boolean Networks: Logic Synthesis and Verification Using Testing Techniques. Springer, 1997.
 
評量方式
(僅供參考)
    
課程進度
週次
日期
單元主題
Week 01
 09/22  Introduction; ABC Tutorial 
Week 02
 09/29  Boolean Algebra 
Week 03
 10/06  Representations of Boolean Functions (1/2) 
Week 04
 10/13  Representations of Boolean Functions (2/2) 
Week 05
 10/20  SOPs and Incompletely Specified Functions (1/2) 
Week 06
 10/27  SOPs and Incompletely Specified Functions (2/2) 
Week 07
 11/03  Two-Level Logic Minimization (1/2) 
Week 08
 11/10  Two-Level Logic Minimization (2/2) 
Week 09
 11/17  Midterm Exam 
Week 10
 11/24  Multi-Level Logic Minimization (1/2) 
Week 11
 12/01  Multi-Level Logic Minimization (2/2) 
Week 12
 12/08  Logic Flexibility 
Week 13
 12/15  Technology Mapping 
Week 14
 12/22  Timing Analysis and Optimization 
Week 15
 12/29  Sequential Circuit Optimization 
Week 16
 01/05  Final Quiz; Project Presentation 
Week 17
 01/12  Equivalence and Property Verification 
Week 18
 01/19  Reversible and Quantum Circuit Synthesis